% Branch, possibly conditionally % #1 The branch condition to use inhibit_i inhibit_i inhibit_i inhibit_i % Move PC to J register ld_j sel_pc sel_pc % J register now points to low part of % jump address. Move address to INC register and % read low jump address into PC_LO sel_j ld_inc sel_mem ld_lo_pc sel_j sel_mem % Increment register now points to high part of % jump address. Move address to J register and % read high jump address to PC_HI sel_inc ld_j sel_mem ld_hi_pc sel_inc sel_mem % Load inc register with address from J register ld_inc sel_j sel_j % Now INC holds the address of the instruction % following the jump, I.e. the address that % should go into PC if jump is *not* to be done. % Otherwise, if jump is OK, PC already contains % the destination address. So what we need here % is a conditional load of PC from INC ld_c_pc sel_inc #1 sel_inc #1 0 reset inhibit_i