%  Load Literal into Register
%  #1   the 8-bit load line to raise (ld_a, ld_b, ld_c)

inhibit_i
inhibit_i
inhibit_i
inhibit_i
ld_inc   #1   sel_mem            sel_pc
              sel_mem            sel_pc
                        ld_pc    sel_inc
                                 sel_inc
0
reset inhibit_i